1. Field of the Invention
The present invention relates to the field of digital signal processing systems, in particular, digital signal processing systems comprising cascaded signal processing units. More specifically, the present invention relates to controlling signal timing for the cascaded signal processing units.
2. Background
In a digital signal processing system, digitized signals are often processed serially by a number of digital signal processing units in a cascaded manner. Within each digitized signal processing unit, as the digitized signals undergo processing, certain amount of timing delays are usually incurred. The delays may be inherent, due to the construction or process of the unit, or preprogrammed. In order for the eventual output to be generated in a fixed, predetermined timing relationship relative to an external reference, signal timing in the signal processing units must be advanced in a coordinated manner. Traditionally, each signal processing unit provides its own circuitry for timing control, delay equalization, and timing derivation; and the signal path is predetermined.
Typically, each signal processing unit provides a "Genlock" circuit to control the timing of its signal generator. A "Genlock" circuit takes an external reference signal and regenerates the signal being processed with a timing advance to compensate for delays in signal processing and propagation. Typically, each signal processing unit also provides its own local memory for equalization of signal delays. For digital signal processing systems whose reference signals are composite reference signals of various timing components, for example, video systems, where reference signals are usually composite signals of the horizontal, vertical, and frame timings, typically each signal processing unit also provides its own "Sync Separator" circuits to derive the various timing components.
These traditional approaches are not very cost effective, since the individual signal processing units have the burden of providing their own circuitry for timing control, delay equalization and timing derivation. In particular, having more than one signal processing units deriving the timing components from a composite reference signal is very costly, since reliable and accurate derivation of timing components from a composite reference signal can be very complex.
Additionally, these digital signal processing systems typically have limited flexibility in reconfiguring their signal paths. Reconfiguration is possible only if the individual signal processing units are padded with additional fixed delays. Even then, reconfiguration is limited to those changes involving simple delays, such as frame delays in a video system.
Thus, it is desirable to have an approach to control the signal timing of cascaded signal processing units of a digital signal processing system where the individual signal processing units do not have the complete burden of providing their own circuitry for timing control, delay equalization and timing derivation. Furthermore, it is desirable if the approach can provide improved flexibility in reconfiguring the signal path.
As will be disclosed, these desired objects and results are among the objects and results achieved by the method and apparatus of the present invention for controlling signal timing of reconfigurable cascaded signal processing units in a digital signal processing system.